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november 2003 pcc028-02a rev 1.1 a lliance semiconducto r 2575 , au g ustine drive ? santa clara , ca ? ? ? www.alsc.com notice: the information in this docum ent is subject to change without notice. 3.3v zero delay buffer general features ? 20 mhz to 70mhz operating range, compatible with cpu and pci bus frequencies. ? zero input - output propagation delay ? multiple low-skew outputs ?output-output skew less than 250 ps ?device-device skew less than 700 ps ?one input drives 9 outputs, grouped as 4 + 4 + 1 ? less than 200 ps cycle-to-cycle jitter is compatible with pentium ? based systems ? test mode to bypass pll ? available in 16-pin, 150-mil soic, 4.4 mm tssop and 150-mil ssop packages ? 3.3v operation, advanced 0.35 cmos technology ? ?spreadtrak?. functional description the pcc028-02a is a low-cost 3.3v zero delay buffer designed to distribute high-speed clocks and is available in a 16-pin soic package. all parts have on- chip plls that lock to an input clock on the ref pin. the pll feedback is on-chip and is obtained from the clkout pad. the pcc028-02a has two banks of four outputs each, which can be controlled by the select inputs as shown in the select input decoding table. if all the output clocks are not required, ba nk b can be three-stated. the select input also allows the input clock to be directly applied to the outputs for chip and system testing purposes. the pcc028-02a pll shuts down in one case, as shown in the select input decoding table. multiple pcc028-02a devices can accept the same input clock and distribute it. in this case the skew between the outputs of the tw o devices is guaranteed to be less than 700ps. all outputs have less than 200 ps of cycle-to-cycle jitter. the input to output propagat ion delay is guaranteed to be less than 350 ps, and the output to output skew is guaranteed to be less than 250ps. block diagram
november 2003 pcc028-02a rev 1.1 3.3v zero-delay buffer 2 of 13 notice: the information in this docum ent is subject to change without notice. select input decoding for pcc028-02a s2 s1 clock a1 - a4 clock b1 - b4 clkout 1 output source pll shut-down 0 0 three-state thr ee-state driven pll n 0 1 driven three-st ate driven pll n 1 0 driven driven driven reference y 1 1 driven driven driven pll n notes: 1. this output is driven and has an internal feedback for the pll. the load on this output can be adjusted to change the skew b etween the reference and the output zero delay and skew control all outputs should be uniformly loaded to achieve zero delay between the input and output. since the clkout pin is the internal feedback to the pll, its relative loading can adjust the input-output delay. for applications requiring zero input-output delay, all outputs, including clkout, must be equally loaded. even if clkout is not used , it must have a capacitive load equal to that on other outputs, for obtaining zero- input-output delay. ?spreadtrak? many systems being designed now utilize a technology called spread spectrum fr equency timing generation. pcc028-02a is designed so as not to filter off the spread spectrum feature of the reference input, assuming it exists. when a zero delay buffer is not designed to pass the spread spectrum feature through, the result is a significant amount of tracking skew which may cause problems in the systems requiring synchronization. pin configuration 1 2 3 4 5 6 7 89 10 11 12 13 14 15 16 ref clka1 clka2 clka3 clka4 clkb1 clkb2 clkb 3 clkb4 v dd gnd s2 clkou t s1 gnd v dd pcc028-02a pcc028-02a
november 2003 pcc028-02a rev 1.1 3.3v zero-delay buffer 3 of 13 notice: the information in this docum ent is subject to change without notice. pin description pin # pin name description 1 ref input reference frequency, 5v-tolerant input 2 clka1 buffered clock output, bank a 3 clka2 buffered clock output, bank a 4 v dd 3.3v supply 5 gnd ground 6 clkb1 buffered clock output, bank b 7 clkb2 buffered clock output, bank b 8 s2 2 select input, bit 2 9 s1 2 select input, bit 1 10 clkb3 buffered clock output, bank b 11 clkb4 buffered clock output, bank b 12 gnd ground 13 v dd 3.3v supply 14 clka3 buffered clock output, bank a 15 clka4 buffered clock output, bank a 16 clkout buffered output, internal feedback on this pin notes: 2. weak pull-up on these inputs
november 2003 pcc028-02a rev 1.1 3.3v zero-delay buffer 4 of 13 notice: the information in this docum ent is subject to change without notice. absolute maximum ratings parameter min max unit supply voltage to ground potential -0.5 +7.0 v dc input voltage (except ref) -0.5 v dd + 0.5 v dc input voltage (ref) -0.5 7 v storage temperature -65 +150 c max. soldering temperature (10 sec) 260 c junction temperature 150 c static discharge voltage (per mil-std-883, method 3015) 2000 v note: these are stress ratings only and are not implied for functi onal operation. exposure to abs olute maximum ratings for prol onged time can affect device reliability. operating conditions for pcc028-02asc-xx commercial temperature devices parameter description min max unit v dd supply voltage 3.0 3.6 v t a operating temperature (amb ient temperature) 0 70 c c l load capacitance, below 100 mhz tbd pf c in input capacitance tbd pf
november 2003 pcc028-02a rev 1.1 3.3v zero-delay buffer 5 of 13 notice: the information in this docum ent is subject to change without notice. electrical characteristics for pcc028-02asc-xx commercial temperature devices parameter description test conditions min max unit v il input low voltage 3 0.8 v v ih input high voltage 3 2.0 v i il input low current v in = 0v 50.0 a i ih input high current v in = v dd 100.0 a v ol output low voltage 4 i ol = 8ma 0.4 v v oh output high voltage 4 i ol = -8ma 2.4 v i dd supply current unloaded outputs at 66.67 mhz, sel inputs at v dd 32.0 ma switching characteristics for pcc028-02asc-1 commercial temperature devices 5 parameter description test conditions min typ max unit 1/t 1 output frequency 30-pf load 20 70 mhz duty cycle 4 = (t 2 / t 1 ) * 100 measured at 1.4v, f out = 66.67 mhz 40.0 50.0 60.0 % t 3 rise time 4 measured between 0.8v and 2.0v 2.50 ns t 4 fall time 4 measured between 2.0v and 0.8v 2.50 ns t 5 output-to-output skew 4 all outputs equally loaded 250 ps t 6 delay, ref rising edge to clkout rising edge 4 measured at v dd /2 0 350 ps t 7 device-to-device skew 4 measured at v dd /2 on the clkout pins of the device 0 700 ps t 8 output slew rate 5 measured between 0.8v and 2.0v using test circuit #2 1 v/ns t j cycle-to-cycle jitter 4 measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time 4 stable power supply, valid clock presented on ref pin 1.0 ms
november 2003 pcc028-02a rev 1.1 3.3v zero-delay buffer 6 of 13 notice: the information in this docum ent is subject to change without notice. switching characteristics for pcc028-02asc-1 industrial temperature devices 5 parameter description test conditions min typ max unit 1/t 1 output frequency 30-pf load 20 70 mhz duty cycle 4 = (t 2 / t 1 ) * 100 measured at 1.4v, f out = 66.67 mhz 40.0 50.0 60.0 % duty cycle 4 = (t 2 / t 1 ) * 100 measured at 1.4v, f out < 50.0 mhz 45.0 50.0 55.0 % t 3 rise time 4 measured between 0.8v and 2.0v 1.50 ns t 4 fall time 4 measured between 2.0v and 0.8v 1.50 ns t 5 output-to-output skew 4 all outputs equally loaded 250 ps t 6 delay, ref rising edge to clkout rising edge 4 measured at v dd /2 0 350 ps t 7 device-to-device skew 4 measured at v dd /2 on the clkout pins of the device 0 700 ps t 8 output slew rate 5 measured between 0.8v and 2.0v using test circuit #2 1 v/ns t j cycle-to-cycle jitter 4 measured at 66.67 mhz, loaded outputs 200 ps t lock pll lock time 4 stable power supply, valid clock presented on ref pin 1.0 ms notes: 3. ref input has a threshold voltage of v dd /2 4. parameter is guaranteed by design and charac terization. not 100% tested in production 5. all parameters specified with loaded outputs.
november 2003 pcc028-02a rev 1.1 3.3v zero-delay buffer 7 of 13 notice: the information in this docum ent is subject to change without notice. switching waveforms t 1 t 2 1.4 v 1.4 v 1.4 v v dd /2 t 6 input output v dd /2 v dd /2 t 7 clkout, device 1 v dd /2 clkout, device 2 duty cycle timing 1.4 v t 5 output output all outputs rise/fall time output - output skew input - output propagation device - device skew
november 2003 pcc028-02a rev 1.1 3.3v zero-delay buffer 8 of 13 notice: the information in this docum ent is subject to change without notice. 1k ? 10 pf v dd gnd outputs clk out c load 0.1 f 1k ? 0.1 f 0.1 f 0.1 f v dd v dd v dd gnd gnd gnd outputs test circuit #1 test circuit #2 for parameter t 8 (output slew rate) test circuits
november 2003 pcc028-02a rev 1.1 3.3v zero-delay buffer 9 of 13 notice: the information in this docum ent is subject to change without notice. e h a a1 a2 d e b l c h seating plane d 0.004 pi n 1 id 1 8 916 package information: 16-lead (150 mil) molded soic s16 dimensions in inches dimensions in millimeters min max min max a 0.061 0.068 1.55 1.73 a1 0.004 0.0098 0.102 0.249 a2 0.055 0.061 1.40 1.55 b 0.013 0.019 0.33 0.49 c 0.0075 0.0098 0.191 0.249 d 0.386 0.393 9.80 9.98 e 0.150 0.157 3.81 3.99 e 0.050 bsc 1.27 bsc h 0.230 0.244 5.84 6.20 h 0.010 0.016 0.25 0.41 l 0.016 0.035 0.41 0.89 0 8 0 8
november 2003 pcc028-02a rev 1.1 3.3v zero-delay buffer 10 of 13 notice: the information in this docum ent is subject to change without notice. d eh d a a1 b e l c a2 pin 1 id 1 8 916 seating plane package information: 16-lead thin shrunk small outline package (4.40-mm body) dimensions in inches dimensions in millimeters min max min max a 0.043 1.10 a1 0.002 0.006 0.05 0.15 a2 0.003 0.37 0.85 0.95 b 0.007 0.012 0.19 0.30 c 0.004 0.008 0.09 0.20 d 0.193 2.008 4.90 5.10 e 0.169 0.177 4.30 4.50 e 0.026 bsc 0.65 bsc h 0.246 0.256 6.25 6.50 l 0.020 0.028 0.50 0.70 0 8 0 8
november 2003 pcc028-02a rev 1.1 3.3v zero-delay buffer 11 of 13 notice: the information in this docum ent is subject to change without notice. d e h a a1 b c d e l 0. 00 4 pin 1 id seating plane 1 8 9 16 package information: 16-lead (150-mil) ssop dimensions in inches dimensions in millimeters symbol min max min max a 0.049 0.065 1.245 1.651 a1 0.004 0.010 0.102 0.254 b 0.008 0.012 0.203 0.305 c 0.007 0.010 0.178 0.254 d 0.189 0.197 4.801 5.004 e 0.150 0.157 3.81 3.988 e 0.025 bsc 0.635 bsc h 0.228 0.244 5.791 6.198 l 0.016 0.050 0.406 1.27 0 8 0 8
november 2003 pcc028-02a rev 1.1 3.3v zero-delay buffer 12 of 13 notice: the information in this docum ent is subject to change without notice. ordering codes licensed under us patent #5,488,627, # 6,646,463 and #5,631,920. ordering code package name package type operating range pcc028-02a sc-1 s16 16-pin 150 - mil soic commercial pcc028-02a si-1 s16 16-pin 150 - mil soic industrial pcc028-02a zc-1 z16 16-pin 4.4mm tssop commercial pcc028-02a zi-1 z16 16-pin 4.4mm tssop industrial pcc028-02a oc-1 o16 16-pin 150 - mil ssop commercial pcc028-02a oi-1 o16 16-pin 150 - mil ssop industrial
november 2003 pcc028-02a rev 1.1 3.3v zero-delay buffer 13 of 13 notice: the information in this docum ent is subject to change without notice. ? copyright 2003 alliance semiconductor corporation. all rights reserved. our three-point logo, our name and intelliwatt are tr ademarks or registered trademarks of alliance. all other brand and product names may be th e trademarks of their respective companies. alliance reserve s the right to make changes to this document and its products at any time without no tice. alliance assumes no responsibility for any errors that ma y appear in this document. the data contained herein represents alliance's best data and/or estimates at the time of issuance. alliance reserves the right to change or correct this data at any time, without not ice. if the product described herein is under development, significant changes to the se specifications are possible. the information in this product data sheet is int ended to be general descriptive info rmation for potential customers and users, and is not intended to operate as, or provide, any guarantee or warrantee to any user or customer. alliance does not assume any responsibi lity or liability arising out of the application or use of any pro duct described herein, and disclaims any expre ss or implied warranties related to the s ale and/or use of alliance products including liability or warranties related to fitness fo r a particular purpose, merchantability, or infringement of any intellectual property rights, except as express agreed to in alliance's te rms and conditions of sale (which are available from alliance). all sales of allian ce products are made exclusively according to alliance's terms and conditions of sale . the purchase of products from alliance does not convey a lice nse under any patent rights, copyrights; mask works rights, trademarks, or any other intellectual property rights of alliance or third parties. alli ance does not authorize its products for use as critical components in life-supporting system s where a malfunction or failure may reasonably be expected to result in significant injury to the user, and the inclusion of alliance products in su ch life-supporting systems imp lies that the manufacturer assume s all risk of such use and agrees to indemnify alliance against all claims arising from such use. alliance semiconductor corporation 2575, augustine drive, santa clara, ca 95054 tel# 408-855-4900 fax: 408-855-4999 www.alsc.com copyright ? alliance semiconductor all rights reserved preliminary information part number: pcc028-02a document version: v1.1 note: this product utilizes us patent # 6, 646,463 impedance emulator patent issued to dan hariton / alliance semiconductor, dat ed 11-11-2003

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